The preset invention relates to a semiconductor device and a manufacturing method for the same. In particular, the present invention is directed to an insulated gate field effect transistor (TFT) formed on an insulating surface, for example, a surface of an insulating substrate such as glass, or an insulating film such as silicon oxide formed on a silicon wafer. Also, the present invention is advantageous for the formation of an insulated gate field effect transistor, especially of an N-channel type, which is driven at a relatively high voltage. It is also to be understood that the present invention is further advantageous for the formation of a TFT on a glass substrate of which glass transition temperature (i.e. distortion point) is 750xc2x0 C. or lower.
Moreover, the present invention is related to an active matrix of a liquid crystal device, a driving circuit of an image sensor or a three dimensional integrated circuit (hybrid IC) using the foregoing semiconductor devices.
In the prior art, TFTs have been known for driving an active-matrix type liquid crystal device or an image sensor or the like. Specifically, in place of an amorphous TFT using an amorphous silicon as an active layer, crystalline TFTs having a higher mobility are now being developed in order to increase driving speed. Moreover, TFTs having a high resistivity region (high resistivity drain) in an active region thereof have been proposed in order to further improve the device characteristics and to increase the capability of driving with a higher voltage. The xe2x80x9chigh resistivity regionxe2x80x9d or xe2x80x9chigh resistivity drainxe2x80x9d in the present invention includes an impurity region (drain) having a higher resistivity, a lightly doped drain (LDD), and also an offset region where a gate electrode does not overlap an impurity region.
However, negative charges caused by hot carriers in an N-channel type TFT tend to be trapped in a portion of a gate insulating film close to a drain region so that the conductivity type of the high resistivity region shifts to p-type. As a result, the source/drain current is obstructed.
Also, it is necessary to use a photolithography technique to form a high resistivity region. This means that production yield and a uniformity of characteristics in the obtained TFTs can not be improved.
It is an object of the present invention to improve the quality of TFTs and the manufacturing yield by solving the foregoing problems. Specifically, it is an object of the present invention to prevent degradation caused by hot carriers, and to produce a high resistivity region in a self-aligning manner without using a photolithography process.
It is a further object of the present invention to manufacture a liquid crystal device using the TFTs of the present invention.
It is still another object of the present invention to produce TFTs which have a high resistivity against water which tends to be contained in an interlayer insulator, especially, formed from TEOS gas.
It is still another object of the invention to utilize electrical charges occurring in an interlayer insulating film to stabilize the property of TFTs.
In accordance with the present invention, a TFT comprises an active semiconductor layer including at least source, drain and channel regions, and further a high resistivity region between the source and channel regions and/or the drain and channel regions, wherein a film which is capable of trapping positive charges is formed adjacent to the high resistivity region. FIG. 1 shows a typical example of this structure.
In FIG. 1, an N-region 111 is interposed between a source region 110 having an N-type and a channel region 3. A gate insulating film 104 exists on the N-region 111. Further, a silicon nitride film 114 which is capable of trapping positive ions therein is formed on the source region and the gate insulating film 104. It is to be understood that even if hot electrons are injected into the gate insulating film from the active layer close to the source region, these can be neutralized by the positive charges existing in the silicon nitride film 114. Accordingly, the high resistivity region can function correctly. Also, the TFT shown in FIG. 1 includes an offset region between the channel region 3 and the high resistivity region 111. The offset region is an extension of the channel region and has a same conductivity type as the channel region (intrinsic).